An operational amplifier circuit has a variety of applications in modern electronic devices. For example, the operational amplifier circuit may be used in a driver circuit for driving a display panel, such as a liquid crystal display (LCD) panel. It is common for an operational amplifier to adopt a differential pair as an input stage for receiving input signals. The linear range of the differential pair is affected by the input voltage difference of the differential pair. For example, the relation between the input voltage difference and the loading current (such as the drain current in a MOSFET implemented differential pair) is linear when the input voltage difference is small. However, the relation becomes nonlinear when the input voltage difference is too large. In order to increase the linear range, a known approach is to provide larger bias current for the differential pair, which in turn results in larger power consumption.
FIG. 1 shows a block diagram of an example operational amplifier. The operational amplifier (OP) circuit 10 includes a differential input stage circuit 111, a loading stage circuit 112, and an output stage circuit 131. The differential input stage circuit 111 receives a pair of differential signals including the first input signal Vin1 and the second input signal Vin2. The differential input stage circuit 111 may be configured to convert a voltage difference between the first input signal Vin1 and the second input signal Vin2 to loading currents i1, i2. The loading stage circuit 112 may be configured to convert the loading currents i1, i2 outputted by the differential input stage circuit 111 to an output signal VO. The loading stage circuit 112 may include an active load circuit (such as transistors) and/or a passive load circuit (such as resistors, capacitors, and inductors). The loading stage circuit 112 may also be referred as a gain stage circuit.
The combination of the differential input stage circuit 111 and the loading stage circuit 112 may be referred as the 1st stage OP 11, whose output is defined as a first stage output VO1. The output stage circuit 131 may be referred as the 2nd stage OP 13, whose output is defined as a second stage output VO2. The voltage gain Av of the operational amplifier circuit 10 is the product of the voltage gain Av1 of the 1st stage OP 11 and the voltage gain Av2 of the 2nd stage OP 12 (Av=Av1×Av2). The voltage gain Av1 of the 1st stage OP 11 is the transconductance Gm of the differential input stage circuit 111 multiplied by the output resistance ro of the loading stage circuit 102 (Av1=Gm×ro).
The second stage output VO2 provided by the output stage circuit 131 is a single-ended voltage signal. If the operational amplifier circuit 10 is used in a display device, the output stage circuit 131 may be coupled to a display panel. It should be noted that number of Ops being included in the operational amplifier circuit 10 is not limited, and output of the last stage of the Ops in the operational amplifier circuit 10 is utilized as an output signal Vout. In the example shown in FIG. 1, the operational amplifier circuit 10 includes two stages of OP. In other embodiments, there may be only one stage OP or more than two stages of OP. Because the 2nd stage OP (as well as other 3rd, 4th . . . stage OP) is optional, the main focus in the following description will be on the 1st stage OP 11, including the differential input stage circuit 111 and the loading stage circuit 112.
FIG. 2A shows a circuit diagram of an example differential input stage circuit. In this example, the differential input stage circuit 111 of the operational amplifier circuit 10 includes two n-type metal-oxide-semiconductor field-effect transistor (NMOS) transistors M01 and M02 and a current source Iss. The current source Iss is coupled to a ground terminal Gnd. The two NMOS transistor Min1 and Min2 have equal gate width and equal gate length. The current value provided by the current source Iss is I. Transistor Min1 receives the first input signal Vin1, and transistor Min2 receives the second input signal Vin2. Being defined as input transistors, transistors Min1 and Min2 in the differential input stage circuit 111 operate in the saturation region.
In order to discuss the operation of the input transistors Min1 and Min2, two types of linearity enhancement circuit are provided in the present disclosure, namely, a bias control circuit and a voltage maintaining circuit. Basically, the bias control circuit is used to reduce the variance range of the loading current being affected by variance of the coupled in between the current source and an input circuit, and the voltage maintaining circuit is coupled in between the loading stage circuit and the input circuit.
The loading currents i1 and i2 flowing through these two input transistors Min1 and Min2 may be represented by the following formulas:
                              i          1                =                              1            2                    +                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                                  I                  SS                                                      ⁢                          (                                                Δ                  ⁢                                                                          ⁢                                      v                    in                                                  2                            )                        ⁢                                          1                -                                                                            (                                              Δ                        ⁢                                                                                                  ⁢                                                                              v                            in                                                    /                          2                                                                    )                                        2                                                                              I                      /                                              μ                        n                                                              ⁢                                          C                      ox                                        ⁢                                          W                      L                                                                                                                              (                              Eq            .                                                  ⁢            1                    ⁢          A                )                                          i          2                =                              1            2                    -                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                                  I                  SS                                                      ⁢                          (                                                Δ                  ⁢                                                                          ⁢                                      v                    in                                                  2                            )                        ⁢                                          1                -                                                                            (                                              Δ                        ⁢                                                                                                  ⁢                                                                              v                            in                                                    /                          2                                                                    )                                        2                                                                              I                      /                                              μ                        n                                                              ⁢                                          C                      ox                                        ⁢                                          W                      L                                                                                                                              (                              Eq            .                                                  ⁢            1                    ⁢          B                )            
where μn is the charge-carrier effective mobility, W is the gate width of the NMOS transistor Min1, L is the gate length of the NMOS transistor Min1, Cox is the gate oxide capacitance per unit area, and Δvin is the input voltage difference, Δvin=Vin1−Vin2. Based on Eq. 1A and Eq. 1B, when
                                                        v              id                        2                    ⪡                                    1                                                μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                                                    ,                            (                  Eq          .                                          ⁢          2                )            the loading currents i1 and i2 may be approximately represented as a linear relation as follows:
                              i          1                =                              I            2                    +                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                                  I                  SS                                                      ⁢                          (                                                Δ                  ⁢                                                                          ⁢                                      v                    in                                                  2                            )                                                          (                              Eq            .                                                  ⁢            3                    ⁢          A                )                                          i          2                =                              I            2                    -                                                                      μ                  n                                ⁢                                  C                  ox                                ⁢                                  W                  L                                ⁢                                  I                  SS                                                      ⁢                          (                                                Δ                  ⁢                                                                          ⁢                                      v                    in                                                  2                            )                                                          (                              Eq            .                                                  ⁢            3                    ⁢          B                )            
That is, when the condition in Eq. 2 is satisfied, the relation between the loading currents i1, i2 and the input voltage difference ΔVin is linear. The transconductance Gm of the differential pair shown in FIG. 2A is:
                              G          m                =                                            i              1                                      Δ              ⁢                                                          ⁢                                                v                  in                                /                2                                              =                                                    μ                n                            ⁢                              C                ox                            ⁢                              W                L                            ⁢                              I                SS                                                                        (                  Eq          .                                          ⁢          4                )            
Although the above analyses are based on the operation of the differential input pair having NMOS transistors, analyses for the differential input pair having PMOS transistors are similar and not redundantly illustrated.
FIG. 2B shows a diagram illustrating a transconductance of the differential input stage circuit shown in FIG. 2A. The horizontal axis is the input voltage difference ΔVin. The transconductance Gm is relatively stable when the input voltage difference ΔVin is small, and hence there is a linear transfer relation between the loading currents i1, i2 and the input voltage difference ΔVin. When the input voltage difference ΔVin becomes larger, the transconductance Gm decreases, and the transfer relation becomes nonlinear. When the input voltage difference ΔVin, exceeds +ΔV1 (or less than −ΔV1), the transconductance Gm becomes 0, and hence the differential pair does not worker properly under such input voltage condition.
Normally, the input transistors Min1, Min2 are desired to operate in the saturation region. For transistors operate in the saturation region, whose drain current and gate-source voltage Vgs are non-linear. Under the circumstance that channel length modulation effect can be neglected, the drain currents of the input transistor Min1 and the second input transistor Min2 and the input voltage difference ΔVin can be represented by Eq. 5. In FIG. 2, the drain currents of the first input transistor Min1 and the input transistor Min2 are equivalent to the loading currents i1, and i2, respectively.
                              Δ          ⁢                                          ⁢                      V                          i              ⁢                                                          ⁢              n                                      =                                            V                              i                ⁢                                                                  ⁢                n                ⁢                                                                  ⁢                1                                      -                          V                              i                ⁢                                                                  ⁢                n                ⁢                                                                  ⁢                2                                              =                                                                      2                  ⁢                                      i                    1                                                                                        μ                    n                                    ⁢                                      C                    ox                                    ⁢                                      W                    L                                                                        -                                                            2                  ⁢                                      i                    2                                                                                        μ                    n                                    ⁢                                      C                    ox                                    ⁢                                      W                    L                                                                                                          (                  Eq          .                                          ⁢          5                )            
After formula manipulation and simplification, Eq. 5 can be represented as Eq. 6.
                                                        1              2                        ⁢                          μ              n                        ⁢                          C              ox                        ⁢                          W              L                        ⁢                                          (                                                      V                                          i                      ⁢                                                                                          ⁢                      n                      ⁢                                                                                          ⁢                      1                                                        -                                      V                                          i                      ⁢                                                                                          ⁢                      n                      ⁢                                                                                          ⁢                      2                                                                      )                            2                                -                      I            SS                          =                              -            2                    ⁢                                                    i                1                            ⁢                              i                2                                                                        (                  Eq          .                                          ⁢          6                )            
In Eq. 6, the source current Iss is equivalent to summation of the loading currents i1 and i2, that is, (Iss=I1+I2). After formula manipulation and simplification, that is, putting square on both side of Eq. 6 and representing the source current Iss with the loading currents i1 and i2, Eq. 6 can be further conducted to obtain Eq. 7.
                                          i            1                    -                      i            2                          =                              1            2                    ⁢                      μ            n                    ⁢                      C            ox                    ⁢                      W            L                    ⁢                      (                                          V                                  i                  ⁢                                                                          ⁢                  n                  ⁢                                                                          ⁢                  1                                            -                              V                                  i                  ⁢                                                                          ⁢                  n                  ⁢                                                                          ⁢                  2                                                      )                    ⁢                                                                      4                  ⁢                                      I                    SS                                                                                        μ                    n                                    ⁢                                      C                    ox                                    ⁢                                      W                    L                                                              -                                                (                                                            V                                              i                        ⁢                                                                                                  ⁢                        n                        ⁢                                                                                                  ⁢                        1                                                              -                                          V                                              i                        ⁢                                                                                                  ⁢                        n                        ⁢                                                                                                  ⁢                        2                                                                              )                                2                                                                        (                  Eq          .                                          ⁢          7                )            
As i1−i2=ΔID, Vin1−Vin2=ΔVin, the relations between the loading currents i1, i2 and the input voltage difference ΔVin can be obtained, which is shown in FIG. 2C. Moreover, the transconductance (Gm) of the differential input pair is equivalent to calculating the differential of the loading current difference (ΔID=i1−i2) to the input voltage difference ΔVin.
                              G          m                =                                                            ∂                Δ                            ⁢                                                          ⁢                              I                D                                                                    ∂                Δ                            ⁢                                                          ⁢                              V                                  i                  ⁢                                                                          ⁢                  n                                                              =                                    1              2                        ⁢                          μ              n                        ⁢                          C              ox                        ⁢                          W              L                        ⁢                                                                                4                    ⁢                                          I                      SS                                                                                                  μ                      n                                        ⁢                                          C                      ox                                        ⁢                                          W                      L                                                                      -                                  2                  ⁢                                                                          ⁢                  Δ                  ⁢                                                                          ⁢                                      V                                          i                      ⁢                                                                                          ⁢                      n                                        2                                                                                                                                          4                      ⁢                                              I                        SS                                                                                                            μ                        n                                            ⁢                                              C                        ox                                            ⁢                                              W                        L                                                                              -                                      Δ                    ⁢                                                                                  ⁢                                          V                                              i                        ⁢                                                                                                  ⁢                        n                                            2                                                                                                                              (                  Eq          .                                          ⁢          8                )            
When the input voltage difference ΔVin is small,
      Δ    ⁢                  ⁢          V              i        ⁢                                  ⁢        n              ⪡                    2        ⁢                  I          SS                                      μ          n                ⁢                  C          ox                ⁢                  W          L                    is satisfied. Meanwhile, the transconductance (Gm) of the differential input pair can be represented as Eq. 9.
                              G          m                =                                            μ              n                        ⁢                          C              ox                        ⁢                          W              L                        ⁢                          I              ss                                                          (                  Eq          .                                          ⁢          9                )            
According to Eq. 9, when the input voltage difference is small, relation between the loading currents i1, i2 and the input voltage difference ΔVin are linear. However, with increment of the input voltage difference ΔVin, Eq. 8 can no longer be conducted to Eq. 9. Therefore, linearity between the loading currents i1, i2 and the input voltage difference becomes worse. Furthermore, since the current of the current source Iss starts to gather at one of the input transistors Min1, Min2, the transconductance Gm becomes to decrease. In a case that the absolute value of the input voltage difference ΔVin is greater than ΔV1, all the current originating from the current source Iss simultaneously flow to one of the input transistors Min1, Min2, and the differential input pair cannot operate normally, that is, Gm=0. Although the above analyses are based on the operation of the differential input pair having NMOS transistors, analyses for the differential input pair having PMOS transistors can be analogue and not illustrated to avoid redundancy.
FIG. 2C shows a diagram illustrating a relation between the loading currents versus input voltage difference of the differential input stage circuit shown in FIG. 2A. The vertical axis represents the loading current i1, i2 and the horizontal axis represents the input voltage difference ΔVin.
In FIG. 2C, curve Ci1 and curve Ci2 represent the relation between the first and the second loading currents i1, i2 and the input voltage difference ΔVin, respectively. As shown by the curve Ci1, when the input voltage difference ΔVin is in a relatively small range, the first loading current i1 is relatively proportional to the input voltage difference ΔVin and there is a linear transfer relation between variance of the first loading current Δi1 and the input voltage difference ΔVin. As shown by the curve Ci2, when the input voltage difference ΔVin is in a relatively small range, the second loading current i2 is relatively inversely proportional to the input voltage difference ΔVin and there is a negative linear transfer relation between variance of the second loading current Δi2 and the input voltage difference ΔVin.
Alternatively speaking, when the input voltage difference input voltage difference ΔVin becomes larger, the variance degrees of the first loading current i1 and the second loading current i2 decreases, and the transfer relations between the loading currents (i1 and i2) are no longer proportional or inversely proportional to the input voltage difference ΔVin. When the input voltage difference ΔVin exceeds +ΔV1 (or less than −ΔV1), the first loading current i1 and the second loading current i2 basically remain constant, and hence the differential pair does not work properly under such input voltage condition.
The linear range of a differential pair is especially important for the operational amplifier circuit in a LCD driver circuit. When the input voltage difference of the differential pair exceeds the linear range, the output signal may deviate from the desired value, and hence the image quality provided by the LCD panel is degraded. Therefore, it is an important subject in the industry to design an operational amplifier circuit with extended linear range.